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White Papers

  • Carlos Santos, Jorge Fernandes, Marcelino Santos and Ricardo Martins

    Paving the Way for the Electronic Design Automation of Power Management Units

  • Diogo Domingos, Marcelino Santos

    In applications that can take advantage of their characteristics, asynchronous circuits (ACs) can have several benefits over synchronous implementations, such as lower power consumption and better modularity. Mixed Signal Power Management (PM) controllers are an example application that greatly benefits from the use of ACs. Nonetheless, due to the difficulty associated with using asynchronous design tools, many designers still resort to synchronous circuits or to ad hoc strategies in the design of these controllers, often leading to inefficient implementations. This paper details the step-by-step application of a design flow for ACs using Signal Transition Graphs (STGs). A guideline for converting a typical state diagram specification to a STG is given, as well as design considerations and solutions for frequent problems when using STG based tools, with the aim of facilitating their adoption. A novel tool that generates self-testing Verilog code based on STG traces is introduced, facilitating testing of the synthesized circuits.

  • Carlos Santos, Jorge Fernandes, Marcelino Santos

    This paper presents a method for efficiency optimization for charge pumps using a negative feedback loop to control the gate driving voltage in each transistor. Switching losses can be significantly lowered by reducing the gate voltage swing while only slightly increasing the conduction losses, thus improving the performance of the switched capacitor dc-dc converter. By setting a target output voltage it is possible to use a feedback loop that controls the voltage swing in each power switch where, by reducing their driving voltage, the output resistance is increased, regulating the output voltage to the target value. The proposed methodology is used to optimize the efficiency of a power management unit (PMU) designed by Silicongate in the scope of the pAvIs project.

  • JM Leitão, R Chaves, MB Santos

    As the number of microelectronic circuits populating the world is increasing, so is the number of critical applications relying on their well-function. Nevertheless, ensuring that a circuit complies with the specifications is still a challenge for design and verification engineers. While simulation-based verification stands out as the most widely adopted strategy, it can only offer limited compliance guarantees since it lacks exhaustiveness. Alternatively, formal verification methodologies and, in particular, model checking, provide the means to prove functional correctness. In this work, we walk trough the verification of a clock masking unit using the NuSMV model-checking tool. Finally, we discuss the applicability of this methodology to larger and more complex designs.

  • J Semião, H Santos, R Cabral, MB Santos, P Teixeira

    Internet of Things (IoT) applications present significant challenges regarding security, safe operation and power management. In the hardware part of each IoT device, CMOS memories occupy a significant percentage of the Integrated Circuits’ silicon area. With device scaling down, performance and reliability challenges exist, namely caused by parametric variations such as Process (P), power supply Voltage (V) and Temperature (T) variations and Aging (A) or, in a general perspective, PVTA variations. The purpose of this paper is to present a novel, on-line, PVTA-aware performance sensor for CMOS SRAM memory cells, sensing and signaling performance degradation, caused e.g. by PVTA variations. The detection strategy consists on the active monitoring of the bit lines, during the read and write operations. In the presence of PVTA degradations, read and write operations have slower transitions, which indicate performance degradation, thus increasing the probability of error occurrence. Hence, when transitions do not occur during the expected time frame, an error signal is flagged to the output due to a slow transition. The sensor’s correct operation is demonstrated using SPICE simulations for 65 nm and 22 nm technologies, allowing to show its effectiveness on monitoring performance and aging degradation on SRAM memory blocks.

  • R Capeleiro, JM Leitão, R Chaves, MB Santos

    In security and safety-critical applications, detecting a clock failure may prevent or at least mitigate the consequences of system faults by letting the system enter a backup state when such an alarm is triggered. In this paper, we propose an RC-based frequency monitoring circuit suitable for embedded clock failure detection, focusing on low-power consumption and robustness against environmental and manufacturing variations. The monitor was implemented in GlobalFoundries 22FDX technology and designed to trigger for an input clock frequency lower than a trimmable threshold. When considering a test case of a fail-safe LCD controller, the trimmed frequency threshold of 22 kHz was found to vary less than 1% over PVT corners while consuming only 150 nW

  • RB Capeleiro, MB Santos

    Segment LCD displays are extremely energy efficient, being the simplest form of displaying information in the sub-microamp and even sub-hundred-nanoamp range. They are an attractive solution for ultra-low power circuits that need a user interface. However, high impedance voltage supplies are particularly affected by the switching noise introduced by LCDs. In this paper, a driver topology for statically driven displays that minimizes supply noise and switching losses, implemented in a 22 nm FD-SOI technology, is presented. The proposed solution uses non-overlap MOSFET drivers and a feed-forward method of discharging LCD segments before charging, improving the overall efficiency of the driver from 59.2 % to 95.2 %, when compared with a traditional implementation.

  • MB Santos, IC Teixeira, JP Teixeira

    The Internet of Things (IoT) paradigm is enabling easy access and interaction with a wide variety of devices, some of them self-powered, equipped with microcontrollers, sensors and sensor networks. Low power and ultra-low-power strategies, as never before, have a huge importance in today’s CMOS integrated circuits, as all portable devices quest for the never-ending battery life, but also with smaller and smaller dimensions every day. The solution is to use clever power management strategies and reduce drastically power consumption in IoT chips. Dynamic Voltage and Frequency Scaling techniques can be rewardingly, and using operation at subthreshold power-supply voltages can effectively achieve significant power savings. However, by reducing the power-supply voltage it imposes the reduction of performance and, consequently, delay increase, which in turn makes the circuit more vulnerable to operational-induced delay-faults and transient-faults. What is the best compromise between power, delay and performance? This paper proposes an automatic methodology and tool to perform power-delay analysis in CMOS gates and circuits, to identify automatically the best compromise between power and delay. By instantiating HSPICE simulator, the proposed tool can automatically perform analysis such as: power-delay product, energy-delay product, power dissipation, or even dynamic and static power dissipations. The optimum operation point in respect to the power-supply voltage is defined, for each circuit or sub-circuit and considering subthreshold operation or not, to the minimum power-supply voltage where the delays do not increase too much and that implements a compromise between delay and power consumption. The algorithm is presented, along with CMOS circuit examples and all the analysis’ results are shown for typical benchmark circuits. Results indicate that subthreshold voltages can be a good compromise in reducing power and increasing delays.

  • J Ventura, TH Moita, MB dos Santos

    In the present work the behavior of a Peltier Cell is studied with the purpose of precision temperature control in testing and characterization of thermal sensors. An overview of the state of the art is made and a theoretical model is derived for the real system and two controllers are developed. The first controller, based on the classic PID and a second one employing the linear quadratic regulator applied to the cell. Both controllers are able to reach a precision of 100m°C, a feat unattainable by current thermal chambers. The controllers are firstly simulated then implemented and their performance is compared based on the following figures of merit: time to reach a desired temperature within a threshold, overshoot and above all, steady state error. With the second controller, an error of 5:5m°C in 320 seconds can be achieved in the worst case scenario, an improvement of 3 orders of magnitude over the conventional methods of thermal sensor characterization.

  • PL Ramos, JM da Silva, DR Ferreira, MB Santos

    The design, manufacture and operational characteristics (e.g., yield, performance, and reliability) of modern electronic integrated systems exhibit extreme levels of complexity that cannot be easily modelled or predicted. Different mathematical methodologies have been explored to address this issue. Monte Carlo simulation is the most widely employed and straightforward approach to evaluate the circuits' performance statistics. However, the high number of trial cases and the long simulations times required to obtain results for complex circuits with a ppm resolution, lead to very long analysis times. The present work addresses the evaluation of alternative statistical inference methodologies which allow obtaining similar results departing from a smaller dimension data set of Monte Carlo simulations from which the overall population is estimated. These methodologies include the use of Bayesian inference, Expectation- Minimization, and Kolmogorov-Smirnov tests. Results are presented which show the validity of these approaches.

  • T. Domingues, M. Santos, G. Tavares

    This paper presents a technical solution for a audio player based on Click Modulation, capable of generating a PWM output out of a pre generated audio file. This modulation allows a spurious-free baseband with very low PWM switching rates. The player is based on a Texas Instrument (TI) C2000 32-bit microcontroller, that provides high resolution PWM generation with low system clock and very competitive price. Off-line Click Modulation and typical PWM modulation solutions (NPWM and USPWM) are also reported. In addition, overview of two analytical approaches for PWM spectrum determination and its results are used to help the different process used to generate the tested signals. Also a numerical approach is used for PWM spectrum determination. The experimental results of the off-line modulations used validate the theoretical and the numerical models used.

  • M.S. Pereira, J.E.N. Costa, M. Santos, J.C. Vaz

    This paper presents a low-power and a low output voltage CMOS Bandgap Reference Generator topology with high PSRR and a novel temperature curvature compensation method. The proposed design was implemented in a standard 0.13 μm CMOS process. The main circuit is based in an opamp based β-multiplier bandgap circuit with resistive division. The compensation method cancels out up to 2nd order non-linear terms of the BJT voltage by using the MOSFET leakage current effect. The performance of the circuit was verified by post-layout simulations. Simulated results have shown temperature coefficients as low as -4.4 ppm/°C over a temperature range of 140°C (-40°C to 100°C). In addition the circuit demonstrated a PSSR of -100 dB at low frequencies and -73 dB at 1 MHz. The current consumption is 1.1 μA at 27°C.

  • C. Leong, J. Semião, M.B. Santos, I.C. Teixeira, J.P. Teixeira

    The purpose of this paper is to present a methodology for Field Programmable Gate Array based designs, either to reduce power consumption or to boost performance during product lifetime. The methodology includes a performance sensor, focusing long-term parametric variations like Process, power-supply Voltage, Temperature and Aging, and a Single Event Upsets' sensor, focusing intermittent variations like radiation effects and disturbances. The performance sensor predictively detects errors in critical paths, either allowing power-supply voltage to be reduced, or clock frequency to be raised, creating a dynamic voltage and frequency scaling technique to reduce power or to increase circuit performance. Fault-tolerance is enhanced not only by predictively detecting errors in performance sensors, but also by using of traditional fault-tolerance solutions like Triple-Modular Redundancy or Error Correcting Codes. The Single Event Upsets' sensor monitors Single Event Upsets in Block Random Access Memory, which allows a faster evaluation of radiation effects than the configuration memory monitoring, thus increasing error detection and correction. The Hardware Description Language sensor's functionality is defined by the designer, according to the target circuit configuration in the Field Programmable Gate Arrays' structure. The adaptive scheme uses an Automatic Voltage and Frequency Controller to modify power-supply voltage and/or clock frequency, while still guaranteeing safe operation. The built-in performance sensors monitor performance deviations in pre identified critical paths during circuit operation. The clock frequency increase is made possible by reducing the pessimistic safety margins defined by standard simulation tools to account for variability. The performance sensors delay margins are programmable, so the most adequate delay margin can be used to guarantee safe operation. Conversely, the same performance can be achieved with lower power-supply voltage. Simulation and experimental results with Virtex 5 and Spartan 6 boards show that significant performance improvements (typically, 30%) can be achieved with this methodology.

  • José F Rocha and José Manuel Ferreira das Dores Costa and Marcelino Bicho dos Santos

    In an integrated DC-DC converter, voltage spikes are generated during the commutation of the power switches and they may cause the device malfunction if its magnitude is excessive. That occurs when, targeting high efficiency, very fast switching is implemented in a low voltage CMOS process, with higher impact when the converter output current is high. These conditions that cause spikes of significant magnitude, in the order of Volts, are common in modern DC-DC converters for portable equipment powered by batteries. Magnitude limitation of voltage spikes in hard switching converters is a hot research topic and the known solutions are surveyed here. Resonant switches topologies are frequently mentioned as an alternative to overcome voltage spikes in a DC-DC converter, but generally this solution is dismissed in integrated implementations. This paper investigates if the resonant topologies are an effective solution to overcome voltage spikes during the switches commutation in a buck converter. Two buck DC-DC converters using resonant switches are analyzed, namely a QR-ZCS topology and a QSW- ZVS topology. The analysis proceeds in two steps that can be easily applied to other resonant converters. Results show that resonant DC-DC converters also generate voltage spikes which magnitude is sometimes higher than that generated in a hard switching converter, and is superimposed to the overvoltage occurring in the resonant phase. This is an important result since resonant, or soft switching, converters are occasionally mistakenly mentioned as free of voltage spikes.

  • Abílio Parreira, Floriberto Lima, Marcelino Santos

    This paper presents a solution for controlling integrated DC–DC converters with high switching frequency (>20 MHz). The increase of the switching frequency is a trend biased by output filter volume restrictions and integration demand. The control of DC–DC converters operating at high frequency presents an opportunity to speed up the converter response time but also a challenge specially for the control solution, quiescent current and to limit the sensitivity to process and operating conditions for the mixed signal circuits involved. The solution presented in this work relies on separating the duty-cycle into three parts: a load-free value that depends only on the input and output voltages, a transient fast correction contribution, and an accurate compensation for the IR drop that depends on the load current. The load-free portion of the duty-cycle has a compensation of PVT variations and the fast transient part of the duty-cycle uses a non-linear sliding mode control solution. All the analog blocks required for the implementation of the proposed solution are detailed.

  • Tiago Manuel Oliveira Henriques Moita, Carlos Beltran Almeida and Marcelino Bicho dos Santos

    This paper presents a new methodology that establishes a bridge between the design and the characterization test of mixed-signal integrated circuits. The same interface is used for the simulation, during the design phase, and for the test setup configuration, during the silicon characterization test. The information used for design validation (testbenches) during the design phase is usually not reused in the characterization of the silicon. Moreover, the feedback that designers can obtain from the lab is nowadays limited since generally designers are not familiar with the configuration of the stimulus and the visualization equipment available in the lab. This work originally uses a Cadence® library to bridge design and test, allowing the characterization of integrated circuits through the use of interfaces that are familiar to designers: the testbench schematics used for design validation and the visualization tools used for simulation results. Using this approach, designers can interact with the silicon the same way they do with the circuit simulator. Additionally, this methodology reduces the characterization test preparation cost.

  • Jorge Esteves, João Pereira, Júlio Paisana and Marcelino Santos

    In this paper, a low power, output-capacitor-free, low-dropout regulator (LDO) is proposed with a new dynamic biased, multiloop feedback strategy. Initially, a theoretical macromodel is presented based on the analogy between the capless LDO and the mechanical non-linear harmonic oscillator, enabling to shed new light on the non-linear amplification, dynamic and adaptive biasing techniques used in the multiloop feedback LDO control in the large signal context. To implement some of the unexplored abilities of this model the new capless LDO topology is proposed. The output class AB stage of the error amplifier and the non-linear derivative current amplifier of the LDO feedback loop ensure dynamical extended close-loop bandwidth gain and dynamical damping enhancement for fast load and line LDO transients. Using the new dynamic biasing of the derivative loop, an improvement is obtained in the derivative sensing of the fast output voltage variations, enabling a significant enhancement in the transient response of the capless LDO. The proposed LDO, designed for a maximum current of 50 mA in UMC RF 1P8M 0.13 μm, requires a quiescent current of only 4.1 μA and presents excellent transient response when compared to the state-of-the-art.

  • Valter António Louzeiro Sádio, Fabian Rein, Christian Münker and Marcelino Bicho dos Santos

    This paper presents an accurate new model for the losses related with charge/discharge process in switched capacitor (SC) DC–DC converters, named from now on inherent losses, considering especially the full integration of the converter. The model was developed for a voltage doubler and it is based on the differential equations of the circuit. It is considered that the output capacitor (COUT) has dimensions comparable to the flying capacitors (CFLY). That leads to a more complex, but also more realistic, model of the circuit, especially for fully integrated converters. Usually, in SC DC–DC converters with external capacitors, COUT CFLY, and a simple RC first order model can be used, but for fully integrated SC DC–DC converters, other techniques are applied to lower the voltage ripple instead of just using a large COUT. Simulations of a voltage doubler were performed to be used as reference and to validate the model that is also compared with other models from recent publications. The results showed that this model is more accurate in calculating the power losses of the voltage doubler across a wide range of CFLY and COUT values, being a model with small complexity. Compared to simulation results, the proposed model presents a maximum relative error around 0.13%, while previous models present maximum errors that are, at least, 6%. This modeling is particularly important because it may be used in the optimization of the SC DC–DC converter taking into account the specifications and area limit, if the dynamic losses associated to the parasitic capacitances in the circuit are considered.

  • M. D. Rolo, L. N. Alves, E. V. Martins, A. Rivetti, M. B. Santos, J. Varela

    An analogue CMOS front-end for triggering and amplification of signals produced by a silicon photomultiplier (SiPM) coupled to a LYSO scintillator is proposed. The solution is intended for time-of-flight measurement in compact Positron Emission Tomography (TOF-PET) medical imaging equipments where excellent timing resolution is required ( ≈ 100ps). A CMOS 0.13μmtechnology was used to implement such front end, and the design includes preamplification, shaping, baseline holder and biasing circuitry, for a total silicon area of 500x90 μm. Waveform sampling and time-over-threshold (ToT) techniques are under study and the front-end provides fast and shaped outputs for time and energy measurements. Post layout simulation results show that, for the trigger of a single photoelectron, the time jitter due to the pre-amplifier noise can be as low as 15 ps (FWHM), for a photodetector with a total capacitance of 70 pF. The very low input impedance of the pre-amplifier ( ≈ 5Ω) allows 1.8 ns of peaking time, at the cost of 10 mW of power consumption.

  • Bruno Jacinto, Carlos Moreira and Marcelino Santos

    This work proposes a digital implementation of the Sliding Mode Control law in a DC–DC Buck converter. The control law is implemented monitoring only the DC–DC output voltage, and is capable of producing a maximum overshoot/undershoot of 50 mV for load transients from 0 A to 1.5 A and vice versa. The maximum settling time for these conditions at 1.5% is 5.51 µs for a load transient from 1.5 A to 0.15 A. For line transients the DC–DC converter produces minimal overshoot/undershoot. Results are present for the Matlab® model with the continuous control law and for the final implementation using HSim® with the digital control law implementation. The ADC is implemented using a current controlled delay line and it is insensitive to layout parasitics, temperature, supply voltage and process parameters changes. The ADC self calibration capability is considered a major original contribution of this work. The ADC and the digital control where designed using AMS CMOS technology C35B4 (0.35 µm).

  • Nuno Dias, Marcelino Santos, Ângelo Monteiro, Pedro Braga and Alexandre Neves

    In this paper we propose an optimization method for low power, high-efficiency DC–DC conversion. A detailed analysis of a multi-mode Step-Down (or Buck) converter losses is presented, allowing the comparison of the power MOS channel conduction losses with their gate-driving losses in order to find the optimum gate-driving voltage that maximizes the converter's efficiency. It is shown that the gate-voltage controller can be simplified to a unique voltage value applied below a determined output current, while still achieving efficiencies over 90% at output currents as low as 10 mA. Simulation results of a 600 mA, 2 MHz, Buck commercial converter, implemented in a 65 nm technology are presented validating the developed models and control methodology. A low power (<20 µW) simple adaptive timing circuit is proposed to efficiently implement the gate-voltage controller with low complexity, low die area (0.007 mm2), and low quiescent current consumption (<2.4 µA).

  • Ângelo Monteiro, Marcelino Santos, Alexandre Neves and Nuno Dias

    This paper describes the techniques to design low power series low dropout regulators (LDO) with low output noise and high power supply rejection (PSR). The noise analysis of the bandgap reference is critical to the linear regulator's output noise, since it represents the main source of noise. The necessary trade-offs that a designer faces are discussed according to the demands of modern IP cores. A precise theoretical noise analysis of a typical bandgap and LDO topology is presented, allowing the analogue designer to identify which are the trade-offs between power and noise, and decide the architecture and design criteria based on these constraints. A LDO and a bandgap with low noise, low power and high PSR are designed in a 0.35 μm CMOS technology and integrated in a Power Management Unit (PMU). No decoupling capacitor is considered in the reference's output.

  • Nuno Guerreiro, Marcelino Santos, Paulo Teixeira

    Accurate test effectiveness estimation for analogue and mixed-signal Systems on a Chip (SoCs) is currently prohibitive in the design environment. One of the factors that sky rockets fault simulation costs is the number of structural faults which need to be simulated at circuit-level. The purpose of this paper is to propose a novel fault list compression technique by defining a stratified fault list, build with a set of “representative” faults, one per stratum. Criteria to partition the fault list in strata, and to identify representative faults are presented and discussed. A fault representativeness metric is proposed, based on an error probability. The proposed methodology allows different tradeoffs between fault list compression and fault representation accuracy. These tradeoffs may be optimized for each test preparation phase. The fault representativeness vs. fault list compression tradeoff is evaluated with an industrial case study—a DC-DC (switched buck converter). Although the methodology is presented in this paper using a very simple fault model, it may be easily extended to be used with more elaborate fault models. The proposed technique is a significant contribution to make mixed-signal fault simulation cost-effective as part of the production test preparation.

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